The Execution Unit, EU

The execution unit(EU):

The main function of EU is decoding and execution of the instructions. It tells the BIU that where to fetch instructions or data from.

Different Parts of Execution Unit(EU):-

                •ALU

                •Flag Register

                •General Purpose Registers

                •Pointer and Index registers

                •Decoder

                •Control Circuitry

Bus Interface Unit, BIU, Continue........

Instruction Pointer:-

•      It is 16-bit register, which identifies the location of the next word of instruction code that is to be fetched in the current code segment.

•      IP contains an offset instead of the actual address of the next instruction.

•      The 20-bit address produced after addition of the offset stored in IP to segment base address in the CS is called the Physical address of the code byte.

The Queue:-

•      The last section of BIU is the FIFO group of registers called a queue. It is basically a group of registers.

•      This arrangement makes possible for the BIU to fetch the instruction byte while EU is decoding an instruction or executing an instruction which does not require use of buses.

•      This arrangement is called pipelining.

•      This is done to speed up the program execution.

Bus Interface Unit (BIU)

The Bus Interface unit (BIU):-

This unit handles all transfer of data and addresses on the buses for the EU(execution unit). This unit sends out addresses, fetches instructions from memory, reads data from ports and memory and writes data to ports and memory.

Different Parts of BIU:
a.Segment Register
b.Instruction Pointer
c.The Queue


1.)Segment Register:- BIU contains four 16-bit segment registers as follows:

    Code segment (CS) register
    Stack segment (SS) register
    Extra segment (ES) register
     Data segment (DS) register 



Function of Segment Register:-

Ø In 8086 complete 1MB memory is divided into 16 logical segments.
Ø Each segment thus contains 64 KB of memory.
Ø While addressing any location in the memory bank, the Physical address is calculated from two parts, the first part is Segment address, and the second is Offset.
Ø The segment registers contain 16-bit segment base addresses related to different segments.
Ø Thus the CS, DS, ES, SS segment registers, respectively contain the segment addresses for the Code, Data, Extra and Stack segments.
Ø They may or may not be physical separated.
Ø Each segment register contains a 16-bit base address that points to the lowest-addressed byte of that particular segment in memory. 





Memory Address generation:-Now i am going to tell you about how physical memory addresses is determined. For this bus interface unit has used an adder. You will understand the idea for finding the physical address with the help of example.




Generation of physical address:-

          Segment address- 1005H
          Offset address     -  5555H
          Segment address-1005H- 0001 0000 0000 0101
          Shifted by 4-bit positions-0001 0000 0000 0101 0000
                                                +
          Offset address                -           0101 0101 0101 0101
          Physical  address             -0001 0101 0101 1010 0101
                                                        1         5        5       A         5 



Instruction Pointer:-
•      It is 16-bit register, which identifies the location of the next word of instruction code that is to be fetched in the current code segment.
•      IP contains an offset instead of the actual address of the next instruction.
•      The 20-bit address produced after addition of the offset stored in IP to segment base address in the CS is called the Physical address of the code byte.



The Queue:-
•      The last section of BIU is the FIFO group of registers called a queue. It is basically a group of registers.
•      This arrangement makes possible for the BIU to fetch the instruction byte while EU is decoding an instruction or executing an instruction which does not require use of buses.
•      This arrangement is called pipelining.
•      This is done to speed up the program execution.

8086 Microprocessor Internal Architecture Diagram

8086 internal architecture:

BIU (Bus Interface Unit):-
·       It sends out tasks.
·       It fetches instructions from memory.
·       It reads data from memory and ports.
·       It also writes data from memory and ports.
·       So BIU takes care of all the address and data transfers on the buses.



Execution Unit:-
·       It tells the BIU, from where to fetch the instruction or data.
·       It decodes the fetched instructions.
·       It executes the fetched instructions.  
   EU takes care of performing operations on data.

Important Features of 8086 Microprocessor

Basic features:-

1.It is 16 bit processor. So that it has 16 bit ALU, 16 bit registers and internal data bus and 16 bit external data bus. It make s faster processing.

2.It has three version based on the frequency of operation:
a)8086 -> 5MHz
b)8086-2 ->8MHz
c)8086-1 ->10 MHz

3.8086 has 20 bit address lines to access memory. Hence it can access 
                  2^20 = 1 MB memory location.

4.8086 has 16-bit address lines to access I/O devices, hence it can access
                  2^16 = 64K I/O location

5.Pipelining:-8086 uses two stage of pipelining. First is Fetch Stage and the second is Execute Stage.

Fetch stage that prefetch upto 6 bytes of instructions stores them in the queue.
Execute stage that executes these instructions.
Pipelining improves the performance of the processor so that operation is faster.

6.Operates in two modes:-8086 operates in two modes:
a)Minimum Mode: A system with only one microprocessor.
b)Maximum Mode:-A system with multiprocessor.

7.8086 uses memory banks:-The 8086 uses a memory banking system. It means entire data is not stored sequentially in a single memory of 1 MB but memory is divided into two banks of 512KB.

8.Interrupts:-8086 has 256 vectored interrupts.

9.Multiplication And Division:-8086 has a powerful innstrction set. So that it supports Multiply and Divide operation.

Comparison of 8085 and 8086 Microprocessor

There are some of the difference mentioned below:


1.Size:-
 8085 is 8 bit microprocessor whereas 8086 is 16 bit microprocessor.


2.Address Bus:-
8085 has 16 bit address bus and 8086 has 20 bit addres bus.


3.Memory:-
8085 can access upto 2^16 = 64 Kb of memory whereas 8086 can access upto
 2^20 = 1 MB of memory.


4.Instruction Queue:-
8085 doesn't have an instruction queue whereas 8086 has instruction queue.


5.Pipelining:-
8085 does not support pipelined architechture whereas 8086 supports pipelined architechture.


6.Multiprocessing Support:-
8085 does not support multiprocessing support whereas 8086 supports.


7.I/O:-
8085 can address 2^8 = 256 I/O's and 8086 can access 2^16 = 65,536 I/O's


8.Airthmetic Support:-
8085 only supports integer and decimal whereas 8086 supports integer, decimal and ASCII arithmetic.


9.Multiplication and Division:-
8085 doesn't support whereas 8086 supports.


10. Operating Modes:-
8085 supports only single operating mode whereas 8086 operates in two modes.


11.External Hardware:-
8085 requires less external hardware whereas 8086 requires more external hardware.


12.Cost:-
The cost of 8085 is low and 8086 is high.


13.Memory Segmentation:-
In 8085, memory space is not segmented but in 8086, memory space is segmented.

Introduction to 8086 Microprocessor

INTRODUCTION:

8086 is an enhanced version of 8085 that has been developed by Intel in 1976.
It is a 16 bit Microprocessor. It has a powerful instruction set and it is capable to providing multiplication and division operations directly. It has 20 address lines and 16 data lines. So it can access upto 1 MB of memory.
It supports two modes of operation: first is maximum mode and second is minimum mode. Minimum mode is applicable for system that have a single processor and maximum mode is used for the multiprocessor system.
8086 provides an additional features that it has an instruction queue capable to store six instruction bytes from the memory. The next instruction is fetched while the present instruction is being executed. So it makes the processor fast.